2017校招_Digital Verification Engineer
恩智浦（中国）管理有限公司
- 公司规模：10000人以上
- 公司性质：外资（欧美）
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2017-05-26
- 工作地点：苏州
- 招聘人数：若干人
- 工作经验：无工作经验
- 学历要求：本科
- 职位月薪：1-1.5万/月
- 职位类别：IC验证工程师
职位描述
职位描述：
Responsibilities:
1. Main responsible on IP level, subsystem level and SoC level verification for connectivity MCU, MPU which targets IoT application. the verification work includes develop test benches, modeling, assertions/checkers/monitors, test plan and test development and sign off for tape out.
2. Support the IP and SoC design, architecture definition.
3. Join the verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
2. Good language skill in English, passed CET-6.
3. Have knowledge about EDA simulation and synthesis tool as well as VLSI design flow.
4. Good knowledge in Verilog, VHDL, System Verilog, and script language.
5. Good knowledge in RTL code style, full synchronous design style, and knowledge of Design-for-Test (DFT) is a plus.
6. Complex IP/ SOC Design Verification, direct experience in IP/SOC or Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard (PCI-e, USB) is preferred.
7. Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog development.
8. Have knowledge about computer architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer is a plus.
9. Have knowledge of OVM,VMM or UVM is a plus.
10. Have knowledge of Wireless communication ,DSP is a plus.
11. Prefer know-how of ARM or AHB bus system.
12. Prefer experience of formal verification with property scheme, for example SVA (System Verilog Assertion).
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Responsibilities:
1. Main responsible on IP level, subsystem level and SoC level verification for connectivity MCU, MPU which targets IoT application. the verification work includes develop test benches, modeling, assertions/checkers/monitors, test plan and test development and sign off for tape out.
2. Support the IP and SoC design, architecture definition.
3. Join the verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
2. Good language skill in English, passed CET-6.
3. Have knowledge about EDA simulation and synthesis tool as well as VLSI design flow.
4. Good knowledge in Verilog, VHDL, System Verilog, and script language.
5. Good knowledge in RTL code style, full synchronous design style, and knowledge of Design-for-Test (DFT) is a plus.
6. Complex IP/ SOC Design Verification, direct experience in IP/SOC or Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard (PCI-e, USB) is preferred.
7. Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog development.
8. Have knowledge about computer architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer is a plus.
9. Have knowledge of OVM,VMM or UVM is a plus.
10. Have knowledge of Wireless communication ,DSP is a plus.
11. Prefer know-how of ARM or AHB bus system.
12. Prefer experience of formal verification with property scheme, for example SVA (System Verilog Assertion).
职能类别： IC验证工程师
公司介绍
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.
联系方式
- Email：fiona.chen@nxp.com
- 公司地址：西青开发区兴华路15号