北京招聘

职位描述：
工作职责：
Chip level DFT design and integration including SCAN, MBIST and JTAG,
   - Perform ATPG and simulation, to sign off DFT pattern,
   - Work closely with logic design engineers for DFT test coverage improvement,
   - Work closely with product and test engineers to debug and solve DFT pattern failure on tester.
   

   - 芯片级DFT设计与集成，包括SCAN, MBIST和JTAG，
   - 负责DFT测试向量的自动生成及仿真，
   - 与逻辑设计工程师紧密合作，提高DFT测试覆盖率，
   - 与产品工程师和测试工程师紧密合作，调试并解决在测试机上失败的DFT测试向量。


任职资格：
Bachelor degree or above in Electronic Engineering or equivalence,
Ø - 3 or more years experience in IC DFT design,
Ø - Familiar with Verilog,
Ø - Familiar with mainstream Simulation tools (VCS, NC or others),
Ø - Familiar with mainstream DFT tools (Mbist, TMB, TestKompress, EncounterTest or others),
Ø - Familiar with mainstream Synthesis, STA, Formal tools are big plus,
Ø - Knowledge on scripting languages in Unix/Linux (csh, Perl, Tcl, phthon or others),
Ø - Fluent in English reading and writing (CET4 or above is desired),
Ø - Good teamwork spirit,
Ø - Capable of handling multiple tasks at one time and have strong sense of responsibility.
Ø - 电子工程本科及以上学历，
Ø - 两年或以上的IC DFT设计经验，
Ø - 熟悉Verilog编程语言，
Ø - 熟悉主流的仿真工具(VCS, NC, 或其它)，
Ø - 熟悉主流的DFT工具(Mbist, TMB, TestKompress, EncounterTest 或其它)，
Ø - 熟悉主流的综合工具，静态时序分析工具，形式验证工具者优先，
Ø - 具有Unix/Linux下的脚本语言编程知识(csh, Perl, Tcl, python或其它)，
Ø - 良好的专业英语读写能力，
Ø - 良好的团队合作精神，
Ø - 拥有同时处理多个任务的能力和敬业精神。 举报 分享

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