北京招聘

职位描述：
Job Title: Staff IP Design Verification Engineer

Location: Beijing/Shanghai

Position Description
Lead or co-lead the IP verification team to finish one IP or subsystem verification, take charge of the verification quality and the schedule

Responsibilities
Lead the IP verification, and decompose the tasks into each team member
Create the testplan and review with team members and designers; make sure the testplan is completed, detailed, and measureable.
Create the random constraint testbench per requirements; make sure team members could implement correctly.
Create the random/direct testcases to cover IP design features, and make sure all required featured was covered.
Debug the testbench and RTL, and report the bug to designer; follow up the whole IP verification status
Finish the verification tasks in time


Qualifications
Education and Experience
Bachelor or above with 6~9 years of work experience


Skills and Knowledge
Verilog/System Verilog
UVM
Perl/Python
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc. experience is an additional plus
ARM related experience is an additional plus 举报 分享

贵州华芯通半导体有限公司

贵州华芯通半导体技术公司由贵州省及美国高通公司共同出资成立，注册地为贵州贵安新区，在北京、上海和贵安新区设有研发运营机构。贵州华芯通半导体专注于设计、开发并销售供中国境内使用的先进服务器芯片。华芯通半导体技术有限公司的成立有助于推动中国集成电路产业发展、提升中国芯片产业开发及设计能力，以及推动并实现中国“强芯梦”。

华芯通半导体2017校园招聘网申地址 http://campus.51job.com/hxt 我们期待你的加入！