Power Analysis and Methodology Engineer
上海奕见企业管理咨询有限公司
- 公司规模：50-150人
- 公司性质：合资
- 公司行业：生活服务
职位信息
- 发布日期：2017-04-16
- 工作地点：上海-浦东新区
- 招聘人数：1人
- 工作经验：2年经验
- 学历要求：本科
- 职位月薪：2.5-3万/月
- 职位类别：集成电路IC设计/应用工程师
职位描述
职位描述：
Power methodology/analysis team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.
What you’ll be doing:
· Develop the power flow to automate the power expenditures measurement.
· Evaluate new low-power technologies and improve chip power efficiency on architectural level.
· Support GPU/TEGRA RTL designers using the power flow and improve their power efficiency on micro-arch level.
· Understand and perform block level and chip-level power analysis.
What we need to see:
· MSEE/MSCS with experiences on ASIC related areas.
· Familiar with advanced low power techniques and high speed clocking desired.
· Experience in low power ASIC design/verification.
· Programming languages: Strong Verilog (or VHDL), Strong scripting languages skills, preferred Perl, Tcl/python/C ++ is a plus.
· Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys Design Compiler, Power Artist is a plus.
Ways to stand out from the crowd:
· Excellent communication skills and ability to be good at teamwork.
· Excellent English writing/speaking skills.
· Strong Perl scripting skills
举报
分享
Power methodology/analysis team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.
What you’ll be doing:
· Develop the power flow to automate the power expenditures measurement.
· Evaluate new low-power technologies and improve chip power efficiency on architectural level.
· Support GPU/TEGRA RTL designers using the power flow and improve their power efficiency on micro-arch level.
· Understand and perform block level and chip-level power analysis.
What we need to see:
· MSEE/MSCS with experiences on ASIC related areas.
· Familiar with advanced low power techniques and high speed clocking desired.
· Experience in low power ASIC design/verification.
· Programming languages: Strong Verilog (or VHDL), Strong scripting languages skills, preferred Perl, Tcl/python/C ++ is a plus.
· Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys Design Compiler, Power Artist is a plus.
Ways to stand out from the crowd:
· Excellent communication skills and ability to be good at teamwork.
· Excellent English writing/speaking skills.
· Strong Perl scripting skills
职能类别： 集成电路IC设计/应用工程师
关键字： 数字硬件设计 perl
公司介绍
上海奕见企业管理咨询有限公司是从事企业管理解决方案的专业咨询服务公司。业务领域涉及各行业，范围覆盖全国一、二线城市，客户包括世界500强知名企业以及各类外资机构驻中国办事处。
联系方式
- 公司地址：地址：span北京市朝阳区建国路118号18层