安顺招聘

职位描述：
主要职责：
-执行整个物理设计过程包括规划/替换/CTS/路由/物理验证
-与前端设计工程师合作以实现区分级和全芯片级的定时关闭
-IO环设计
-串扰分析
-IR降和电源完整性分析
-执行ECO’s
-开发及提高整个芯片级和块级物理设计过程

职位要求：
-本科/硕士电气或计算机编程学位及五年以上物理设计经验
-拥有高级流程，分层设计过程经验
-全芯片/子芯片静态定时分析实践经验。有CPU相关时序收敛背景者更佳
-拥有逻辑综合和同等核对/FV实践经验
-精通物理设计和优化。如：替换，路由，单元格尺寸，缓冲，逻辑结构调整等来改进定时和功率。需要通过ECOs将其实现
-理解DFT逻辑并拥有使用DFT逻辑的封闭设计实践经历。掌握各种模型的DFT定时闭合如：扫描定时和捕获，转换断层，BIST等者更佳
-精通分析和收敛在深亚微米工程中串扰延迟，噪声干扰，电气/制造规则
-理解过程变化效应建模，拥有变化的收敛设计的经验
-拥有关键路径规划和构建经验。有电路，SPICE模拟和/或晶体管级标准经验者更佳
-精通掌握和深入了解工业标准EDA工具
-精通脚本语言比如：Perl, Tcl, Make等。有方法论和/或流程自动化经验者更佳

Key Responsibilities:
- Execute the whole Physical Design flow include Floorplan/Placement/CTS/Routing/Physical Verification
- Work with front end design Engineers to achieve timing closure for both partition level and full chip level
- IO ring design
- Cross talk Analysis
- IR Drop and Power Integrity Analysis
- Execute ECO's.
- Develop and enhance entire physical design flow at both chip and block level.

Requirements:
- BS/MS in Electrical or Computer Engineering with 5+ yrs experience in physical design
- Experience with advanced process, experience with hierachical design flow.
- Hands-on experience in full-chip/sub-chip Static Timing Analysis. CPU related timing convergence background would be a plus.
- Hands on experience in logic synthesis and equivalence checking/FV required.
- Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required. Background in implementing them through ECOs required.
- Understanding of DFT logic and hands-on experience in design closure taking into account DFT logic required. DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc. would be a plus.
- Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes
- Understand process variation effect modeling and experience in design convergence taking into account variations required.
- Experience in critical path planning and crafting. Experience in circuits, SPICE simulations, and/or transistor level STA would be a plus.
- Expertise and in-depth knowledge of industry standard EDA tools required.
- Proficiency in scripting languages, such as, Perl, Tcl, Make, etc. Experience in methodology and/or flow automation would be a plus. 举报 分享

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